BIST Based Interconnect Fault Location for FPGAs

نویسندگان

  • Nicola Campregher
  • Peter Y. K. Cheung
  • Milan Vasilko
چکیده

This paper presents a novel approach to interconnect fault location for FPGAs during power-on sequence. The method is based on a concept known as fault grading which utilizes defect knowledge during manufacturing test to classify faulty devices into different defect groups. A Built-In Self-Test (BIST) method that can efficiently identify the exact location of the interconnect fault is introduced. This procedure forms the first step of a new interconnect defect tolerant scheme that offers the possibility of using larger and more cost effective devices that contain interconnect defects without compromising on performance or configurability.

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Analysis and Evaluation of Routing BIST Approaches for FPGAs

We present stuck-at and bridging fault simulation results for previously proposed Built-In Self-Test (BIST) approaches for the programmable interconnect resources in Field Programmable Gate Arrays (FPGAs). In addition, new BIST approaches are proposed and analyzed via fault simulation. The fault simulation results are used to compare and evaluate the fault detection capabilities and effectivene...

متن کامل

BIST-Based Diagnosis of FPGA Interconnect

We present a Built-In Self-Test (BIST)-based diagnostic approach for the programmable interconnect resources in Field Programmable Gate Arrays (FPGAs) that can be used for either on-line or off-line testing. The technique was originally intended for on-line diagnosis of faulty interconnect to support fault-tolerant applications. However, the technique has been proven to be an excellent approach...

متن کامل

Testing Techniques for Reconfigurable FPGAs

In this paper we discuss the popular testing techniques for reconfigurable FPGAs. For the programmable logic blocks, the array based testing and BIST are covered. For interconnect testing, the bus-based technique and BIST are mentioned. These methods have been compared based on the fault coverage and speed.

متن کامل

BIST-Based Delay-Fault Testing in FPGAs

We present the first delay-fault testing approach for Field Programmable Gate Arrays (FPGAs), applicable for on-line testing as well as for off-line manufacturing and system-level testing. Our approach is based on Built-In Self-Test (BIST), it is comprehensive, and does not require expensive external test equipment (ATE). We have successfully implemented this BIST approach for delay-fault testi...

متن کامل

Embedded Processor Based Fault Injection and SEU Emulation for FPGAs

Two embedded processor based fault injection case studies are presented which are applicable to Field Programmable Gate Arrays (FPGAs) and FPGA cores in configurable System-on-Chip (SoC) implementations. The case studies include embedded hard core and soft core processors which manipulate configuration memory bits to emulate physical and transient faults in the FPGA core including shorts and op...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2004